A flash memory has the data retention period which is short in comparison with other types of memory and remarkably dependent on environmental temperature, and decreases greatly with the rising of temperature. Accordingly, for an apparatus in which a flash memory is installed, a technique for preventing the missing of data in the flash memory, such as refreshing the flash memory periodically, is commonly used to secure the data reliability of the flash memory.
With regard to such refresh processing, Japanese Patent Application Laid-Open Publication (JP-A) No. 2000-11670 discloses an apparatus including a non-volatile memory. The apparatus includes a timer to measure the elapsed time after having performed a writing operation onto the non-volatile memory; a temperature sensor which measures a temperature in the vicinity of the non-volatile memory; a counter which counts the number of times of the writing operation performed onto the non-volatile memory; and a refresh circuit. In the above constitution, the refresh circuit is configured to give weight to the time measured by the timer according to the temperature measured by the temperature sensor and the number of times of the writing operation counted by the counter, and, is further configured to, when the weighted elapsed time measured by the timer exceeds a predetermined time after having performed the weighting, execute the writing operation again on the non-volatile memory.
In recent years, in order to improve an energy saving efficiency, information processing apparatuses generally have multiple operation modes (for example, Ready, Sleep, Power OFF, etc.) corresponding to the usage situations of the apparatuses. In these operation modes, it is expected that a temperature in an apparatus which is working in a certain operation mode is different from that in other operation modes. In particular, in apparatuses equipped therein with a heat source of high calorie, such as a laser beam printer and a MFP (Multi-Function Peripheral), a difference in temperature in the concerned apparatus among the operation modes becomes more appreciable.
In the case where a flash memory is used in an apparatus in which a difference in temperature in the apparatus among operation modes can occur, a large difference occurs in a data retention period of the flash memory among the operation modes depending on the ratio of time periods for which the apparatus has been working in respective operation modes. In view of the above problem, JP-A No. 2000-11670 discloses the technology that a temperature sensor is disposed in an apparatus so as to measure a temperature in the vicinity of the non-volatile memory, an elapsed time is weighted by using the temperature measured by the temperature sensor, and an execution timing of the refresh processing is adjusted. However, the technology of JP-A No. 2000-1670 needs the temperature sensor disposed in the apparatus, which lacks versatility. Further, the technology needs the temperature sensor always driven to measure the temperature, which causes problems about wasteful electricity consumption and an increase of the load on a CPU.
Further, the data retention period of a flash memory lowers also by writing data into the flash memory. If describing concretely, a general flash memory is composed of a MOS (Metal Oxide Semiconductor) transistor (cell) in which a gate electrode is made in a two layer structure. General flash memories can be grouped into NOR type flash memories and NAND type flash memories. In a NOR type flash memory, data can be read, written, erased and rewritten at the single-byte level (that is, a source line and a bit line are connected to each cell). In a NAND type flash memory, data can be read, written, erased and rewritten at the level of plural bytes, in other words, at the block level (that is, multiple bits are serially connected between a source line and a bit line). In any case, by applying a high electric field between a floating gate and a silicon substrate, electrons are made to perform tunneling for a gate insulating film, and injected into a floating gate. With this, information is memorized by utilizing a change of a gate voltage (threshold voltage) at which the MOS transistor changes from an OFF state to an ON state.
Accordingly, if the number of times of writing data for the flash memory increases, the gate insulating film deteriorates due to the tunneling of electrons, the electrons injected into the floating gate are made to escape easily to the silicon substrate, and a data retention period becomes short. In particular, in a NAND type flash memory, data is written at the block level, even when writing is performed on cells in a part of a block, which increases the number of times of the writing data substantially. Thereby, the degradation of the gate insulating film advances and a data retention period becomes short. Then, in the above-mentioned technology of JP-A No. 2000-11670, the number of times of writing data is counted and the elapsed time is weighted by using the counted number. Thereby, an execution timing of the refresh processing is adjusted.
Furthermore, the data retention period of a flash memory lowers also by reading data from the flash memory. For example, in a NAND type flash memory, word lines adjoin to each other and cells connected to the same bit line are connected to each other in a form configured to share a source and a drain. In a reading operation, the selected word lines (control gates) are applied with a low voltage, and the non-selected word lines are applied with a pass voltage higher than a threshold voltage at the time of writing. Accordingly, electrons are made tunneling injection from the silicon substrate into the floating gate of non-selected cells, whereby the threshold voltage of the non-selected cells rises slightly. Therefore, if a reading operation is repeatedly performed for the same cell and an erasing operation is not performed at all, the threshold voltage of the non-selected cells rises gradually, and it becomes difficult to read the right value. As a result, the data retention period becomes short. In this way, although the data retention period becomes also short depending on the number of times of reading data for the flash memory, the technology of JP-A No. 2000-11670 takes only the number of times of writing data into consideration, which hardly carries out an appropriate adjustment of a timing to perform the refresh processing.
In view of such a problem, the execution of the refresh processing at constant intervals in order to secure data reliability is inefficient, and there is fear that the refresh processing itself causes the deterioration of the flash memory (in particular a gate oxide film) and the decrease of the data retention period. That is, in the refresh processing, electrons are extracted from the floating gate by applying high voltage to the silicon substrate side, and then, electrons are injected by applying high voltage to the floating gate side. Accordingly, if the number of times of the application of high voltage increases, the gate oxide film deteriorates, and the data retention period becomes short. Further, by executing the refresh processing, there is also a problem that a large load is applied to a control section to control the refresh processing. The present invention seeks to solve those problems.